The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 1992
Filed:
Aug. 20, 1990
Allen L Solomon, Fullerton, CA (US);
Grumman Aerospace Corporation, Bethpage, NY (US);
Abstract
A multilayer integrated circuit module for supporting integrated circuit chips and for interfacing the chips to external circuitry is disclosed. Each integrated circuit is formed to have conductive contact pads disposed upon beveled edges. The module is comprised of a base layer and a plurality of stacked layers having apertures formed therein and disposed upon the base layer such that at least one well is formed. The aperture defining inclined sidewalls with conductive conduits formed thereon. The inclined sidewalls are formed to support the integrated circuit chips upon the beveled surfaces thereof. The conductive conduits formed on the incline sidewalls contact the integrated circuit chip conductive contact pads. The base layer has conductive conduits formed thereon, the base layer further has vertically inclined surfaces spaced to receive and support the integrated circuit chips along beveled edge portions thereof. The base layer conductive conduits extend along the vertically inclined surfaces and contact the integrated circuit conductive contact pads. Thus, the integrated circuit chips are supported within the wells and are connected to the conductive conduits formed on the base layer and stacked layers solely by means of abutting electrical connection with the chip beveled edge portions. A pattern of conductive conduits formed upon the plurality of stacked layers interfaces the integrated circuit chip to external circuitry. Each of the stacked layers may have a pattern of conductive conduits formed thereon.