Semiconductor memory device with improved address discriminating circuit

Abstract

For accelerating of a testing operation to determine which memory cell in a memory cell array is replaced with a redundant memory cell, a semiconductor memory device is composed of an address discriminating facility having an activation circuit operative to compare an address indicated by an address signal and the address assigned the memory cell replaced with the redundant memory cell for producing a first controlling signal. A testing operation controlling circuit is responsive to a test mode signal for producing a second controlling signal and a data write-in circuit responsive to the second controlling signal and producing a test bit of logic '1' level and a test bit of logic '0' level. The test bit of logic '1' and the test bit of logic '0' are respectively written into the redundant memory cell and the memory cell array so that an address assigned to the memory cell replaced with the redundant memory cell is discriminated through a read-out operation.