The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 1992

Filed:

Jun. 24, 1988
Applicant:
Inventors:

Yukari Watanabe, Itami, JP;

Yuichi Saito, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
3647151 ; 364736 ; 364746 ; 3647365 ;
Abstract

A high-speed encoding apparatus retrieves the bit position of either one of the lowest order bit or the highest order bit having a first logical value. Such retrieving starts from a selected bit-position. The selected bit-position is defined by an input offset value Iofs4:Iofs0. The retrieved bit-position is the output of the encoder Oofs4:Oofs0. A zero detection circuit receives an n-bit data word, segments the n-bits into groups of predetermined length and for each group generates a zero detection when all bits in the group are zero. The zero detection circuit also masks the zero detections according to the high order bit states of the input offset value. A first encoder then generates the high order bits of the apparatus output offset in response to the masked and unmasked zero detections. A second encoder masks one or more of the groups according to the bit states of the input offset value, then generates encoded bit sets for each group. The high order bits of the output offset previously generated then are used to select which of the bit sets are used as the low order bits of the output offset.


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