Composite logic gate circuit with means to reduce voltage required by

Abstract

A logic circuit has a plurality of serially connected logic units wherein each unit is a gate comprising a resistor serially connected to a combination of a plurality of transistors connected together in parallel. The transistors of the logic circuit are arranged to enable reduction of the requisite voltage to be provided by an external power source. By reduction of the voltage, the values of resistance can be reduced without exceeding a power dissipation budget. Alternate logic units, in a series of logic units, are constructed of PNP and NPN transistors. Furthermore, the voltage drop across a transistor of a preceding logic unit, as measured between the emitter and collector terminals of a transistor, is applied, essentially, across the base-emitter junction of a transistor in a succeeding logic unit so as to provide a supply of base current to the transistor of the succeeding logic unit without danger of saturating the transistor and without cutting off current flow to the transistor. Furthermore, the magnitude of resistance of the resistor of the preceding logic unit is sufficient to limit base current to the transistor of the succeeding logic unit so as to avoid saturation of the transistor in the succeeding logic unit. An output signal of the logic unit may be applied to an inverter circuit, and speed-up capacitors may be applied in emitter circuits of the inverter and the preceding logic unit for a sharpening of both leading and trailing edges of a logic signal.