The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 1992
Filed:
Feb. 20, 1991
James R Butler, San Jose, CA (US);
Analog Devices, Inc., Norwood, MA (US);
Abstract
A JFET differential amplifier stage in which the gate-drain voltage of each input JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias current. The input JFETs are cascoded with another pair of JFETs, and the gate-source circuits for the JFETs of each branch are connected in series with the gate-source circuit of an additional JFET between the gates and drains of the input JFETs. The additional JFET is supplied with a current that is substantially less than I.sub.DSS, and thus develops a significant portion of the necessary gate-drain voltages for the input JFETs. This enables a significant net reduction in the chip surface area occupied by the stage.