The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 1992
Filed:
Feb. 28, 1990
John J Talvacchio, Churchill, PA (US);
Westinghouse Electric Corp., Pittsburgh, PA (US);
Abstract
This is a method for making an ohmic connection between a semiconductor and oxide superconductor, the connection being such that current can pass between the semiconductor and the superconductor without going through a degraded portion which is greater than the coherence length of the superconductor. The method can comprise depositing a buffer layer (which is essentially inert to the oxide superconductor) on a first portion of a semiconductor substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer (e.g. of gold or silver) on the oxide superconductor, and depositing a semiconductor contact layer on a second portion of the semiconductor substrate (the semiconductor contact layer being, for example, of aluminum, or a refractory metal silicide); and depositing a layr (e.g. of gold or aluminum) on the semiconductor contact layer and on at least a portion of the superconductor contact layer to electrically connect the semiconductor contact laye and the superconductor contact layer. Alternately, the method can comprise depositing a buffer layer on a first portion of a substrate, and depositing oxide superconductor on the barrier layer, and depositing a superconductor contact layer on the oxide superconductor, and depositing a semiconductor on a second portion of the substrate, and depositing a semiconductor contact layer on the semiconductor, and depositing a layer on the semiconductor contact layer and on at least a portion of the superconductor contact layer to electrically connect the semiconductor contact layer and the superconductor contact layer. Preferably, the superconductor contact layer is of gold, the semiconductor contact layer and the interconnecting layer are of aluminum, and the buffer layer is of zirconium oxide.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile