The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 1992
Filed:
Jul. 27, 1990
Applicant:
Inventors:
Robert B Manley, Ft. Collins, CO (US);
Mark D Crook, Ft. Collins, CO (US);
Assignee:
Hewlett-Packard Company, Palo Alto, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437189 ; 437192 ; 437977 ;
Abstract
A process is described for electrically interconnecting electronic devices located on a surface through one or more planar linking layers consisting of conductors and dielectrics. A three-step additive process is disclosed for forming each planar linking layer. The process may be repeated in order to form the multiple linking layers required for complex VLSI circuits. Each layer is formed by a three step process of applying a uniform dielectric, removing the dielectric where the interconnections, including vias and lines, are to be made and then selectively depositing a conductor to form the interconnections.