The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 1992
Filed:
Mar. 09, 1990
Fujitsu Limited, Kawasaki, JP;
Abstract
A bipolar random access memory comprises a plurality of memory cells arranged in row and column formation, a plurality of word lines provided in correspondence to respective rows of the memory cells, a plurality of bit lines provided in correspondence to respective columns of the memory cells, a row addressing part connected to each of the plurality of word lines, a column addressing part connected to each pair of the adjacent bit lines, a read/write controller supplied with a cell information to be written into an addressed memory cell and further with a read/write control signal indicating whether the random access memory is to be operated in a reading mode or in a writing mode and acting as a current source in the reading and writing modes, a first current control part provided in each column of the memory cells so as to be connected to one of the bit lines in a column selected by the column addressing part at the first side of each of the memory cells, a second current control part provided in each column of the memory cells so as to be connected to the other of the bit lines in the selected colunmn, and a third current control part connected to the first and second current control parts for controlling the first and second current control parts such that the write current in the bit lines connected to the side each of the memory cells to which an information is to be written is increased and such that the write current in the bit lines connected to the side of each of the memory cell to which the information is not written is decreased in the writing mode.