The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 1992
Filed:
Oct. 05, 1990
Hironori Nagasawa, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
In a source-coupled FET logic type output circuit, the drain electrodes of first and second FETs are coupled through a level shift element and load elements to a high-voltage power source, the gate electrodes of the FETs are respectively connected to first and second input terminals, and the source electrodes of these transistors which are coupled together are coupled to a low-voltage power source by a first constant-current power source. Furthermore, between the high-voltage power source and the low-voltage power source, there are connected a third FET with its gate electrode coupled to the drain electrode of the first FET, level shift elements, a second constant-current power source, a fourth FET with its gate electrode coupled to the drain electrode of the second FET, a level shift element, a third constant-current power source, a fifth FET with its gate electrode coupled between the fourth FET and the level shift element, a sixth FET with its gate electrode coupled between the third level shift element and the second constant-current power source, and fifth level shift element. An output signal with the potential corresponding to that of a complementary signal is obtained at an output terminal expending from a connection point between the fifth and sixth FETs.