Branch control in a three phase pipelined signal processor

Abstract

The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of 'hot bits' existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.