The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 14, 1992

Filed:

Jul. 06, 1990
Applicant:
Inventors:

Claudio Contiero, Buccinasco, IT;

Paola Galbiati, Monza, IT;

Lucia Zullino, Milan, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 43 ; 357 34 ; 357 42 ; 357 48 ; 357 52 ;
Abstract

A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming 'well' regions through the collector area. The operation determines the formation of a 'collector extension region' extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between IcIsubstrate is incremented from about 8 to about 300 and the Early voltage from about 20V to about 100V. The V.sub.CEO, BV.sub.CBO and BV.sub.CDES voltages are also advantageously increased by the presence of said 'well' region formed in the collector zone.


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