Digital resolver with a synchronous multiple count generation

Abstract

A digital resolver is provided that accepts an analog representation of an angular or linear displacement within a reticle modulation cycle of a rotatable or translatable member, and provides a highly accurate output digital representation of the displacement within the cycle, even during rapid movement of the member. An encoder cooperative with the interpolator receives an analog signal that represents the displacement, and yields a pair of quadrature-phased sine wave signals accordingly. These signals are provided to the interpolator, wherein each is multiplied by a stored digital representation of a trigonometric function of the output digital signal. The resulting products are then added so as to provide an error signal which is used to drive a digital control loop, such that a digital output signal is provided that represents displacement within a reticle cycle. The control loop includes an up-down counter, and an asynchronous count generator operative to receive the error signal and drive the counter promptly thereafter. Within the asynchronous count generator, no clock signal is employed. Instead, an asynchronous digital circuit promptly provides a count pulse to an appropriate input of the up-down counter, the output providing an accurate digitized representation of the displacement within a reticle cycle of the member. The counter output is also fed back to be multiplied by the quadrature-phased signals.