Data packing circuit in variable length coder

Abstract

A data packing circuit, used in a variable length coder, for receiving code words including variable length codes and code length information of the variable length codes, and packing the variable length codes with no gaps into successive units of bits having predetermined length. The code word is shifted in a first direction by a number of bits equal to a shift number, and in parallel, the code word is shifted in a second direction opposite to the first direction by a number of bits equal to the difference between the predetermined length and the shift number, and zero is filled in each vacant bit which is generated by the above shift operations. The shift number is determined by accumulation of the code lengths by modulo-n addition, n being equal to the predetermined number, and a carry addition of the code lengths whether or not a carry occurs over the above predetermined length in the accumulated value. Logical sums of respective bits of the shifted result in the first direction and corresponding bits of the output of an intermediate date register are obtained. The intermediate data register latches the logical sums in every cycle of the code word when a carry is not detected in the above accumulation, and latches the shifted result in the second direction in every cycle of the code word when the carry is detected. The logical sums are latched as output data of the data packing circuit when the carry occurs.