Digital phase lock loop for a gate array

Abstract

A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having signal inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop. The updates to the delay line achieve steady state by waiting one or more periods of the input signal before the next phase comparison cycle preventing over-correction. The phase correction portion of the cycle is inhibited when the input signal and output signal are less than the predetermined phase difference thereby avoiding possible unnecessary corrections to the phase lock loop. The phase lock loop may be functionally divided among multiple macros in a gate array library and conveniently disposed in the gate array.