Temperature compensated fet power detector

Abstract

A detector for generating an output signal representative of the power of an input signal comprises an input capacitor coupled to receive the input signal for transmitting alternating current portions of the input signal. A first common-source FET pair have gate terminals coupled to a temperature-compensating circuit for varying the gate-to-source voltage. The drain of one FET is coupled through an intermediate capacitor to ground. That drain is also coupled to a relatively positive voltage source through a series-connected inductor and resistor. The drain of the second FET is also coupled to the voltage source through a resistor. An output capacitor couples the alternating current signal, at the junction between the resistor associated with the first transistor and the inductor, to ground. A differential amplifier and comparator generates an output signal representative of the difference between the signals appearing on the transistor sides of the two resistors.