The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 1991

Filed:

Jun. 12, 1989
Applicant:
Inventors:

John H Murphy, Penn Hills, PA (US);

Terry A Jeeves, Penn Hills, PA (US);

Arthur A Anderson, Turtle Creek, PA (US);

Assignee:

Westinghouse Electric Corp., Pittsburgh, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395 10 ; 364736 ; 395 50 ; 395 51 ; 395 61 ; 395-3 ; 395900 ;
Abstract

The present system performs linear transformations on input probabilities and produces outputs which indicate the likelihood of one or more events. The transformation performed is a product of linear transforms such as P.sub.o =[A.sub.j P.sub.j +B.sub.j ].multidot.[A.sub.k P.sub.k +B.sub.k ] where P.sub.j and P.sub.k are input probabilities, P.sub.o is an output event probability and A.sub.j, B.sub.j, A.sub.k and B.sub.k are transformation constants. The system includes a basic processing unit or computational unit which performs a probabilistic gate operation to convert two input probability signals into one output probability signal where the output probability is equal to the product of linear transformations of the input probabilities. By appropriate selection of transformation constants logical and probabilistic gates performing the functions of AND, NAND, OR, NOR, XOR, NOT, IMPLIES and NOT IMPLIES can be created. The basic unit can include three multipliers and two adders if a discrete component hardwired version is needed for speed or a single multiplier/adder, associated storage and multiplex circuits can be used to accomplish the functions of the hardwired version for economy. This basic unit can also be provided as a software implementation, can be implemented as a hardwired decision tree element implementation or implemented as a universal probabilistic processor and provided with a bus communication structure to create expert systems or neural networks suitable for specific tasks. The basic units can be combined to produce a virtual basic building block which has more virtual processors than physical processors to improve processor utilization. The building blocks can be combined into an array to produce either a high speed expert system or a high speed neural network.


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