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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5077676 B1

PDFFull Text
Date of Patent:
Dec. 31, 1991

Filed:

Mar. 30, 1990

Reducing clock skew in large-scale integrated circuits

Applicant:
Inventors:

Charles L Johnson, Rochester, MN (US);

Robert F Lembach, Rochester, MN (US);

Bruce G Rudolph, Rochester, MN (US);

Robert R Williams, Rochester, MN (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorney:

Anglin; J. Michael

Primary Examiner:

Parshotam S Lall

Assistant Examiner:

V N Trans

Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364489 ; 364488 ;
Abstract

In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting the performance (power) of each driver at each level. Where the capacitance of a net is too low to be compensated by a driver, a capacitive terminator is selectively added to that net.

Find Patent Forward Citations

Johnson, Charles. (1991). Reducing clock skew in large-scale integrated circuits (U.S. Patent No. 5077676). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5077676

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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