The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 1991
Filed:
Nov. 28, 1990
Hiroyuki Misawa, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A gate array integrated circuit includes four internal logic circuits each composed of a current mode logic circuit and an emitter follower circuit having an input connected to an output of the current mode logic circuit. One wired logic circuit is formed by interconnecting output terminals of four emitter follower circuits. An one end of an interconnection wiring conductor for interconnecting the output terminals of the four emitter follower circuits is connected to an output terminal of a first emitter follower circuit, and the other end of the interconnection wiring conductor is connected to an output terminal of fourth emitter follower circuit of the N emitter follower circuits. The interconnection wiring conductor serially extends and traces all the output terminals of the four emitter follower circuits from the output terminal of the first emitter follower circuit to the output terminal of the fourth emitter follower circuit without branch, so that the output terminals of the second and third emitter follower circuits are connected to an intermediate portion of the interconnection wiring conductor in the order. A pair of resistors or constant current sources having the same value are connected to only the output terminals of the first and fourth emitter follower circuits, respectively.