The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 1991
Filed:
Jun. 20, 1990
Gerard Boudon, Mennecy, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present logic circuit family is derived from the conventional DCCS logic circuit family. The logic circuit shown in the attached drawing is a six-input AND/NAND. It includes: a logic tree (41) comprised of bottom, middle, and top stages (44, 45, 46) cascoded and dotted at the tree output nodes (OUT, OUT) to perform a determined logic function (F, F). The top stage (46) includes a current switch (49) formed by a pair of input transistors (TX431, TX432) connected in a differential amplifier configuration. The base of one input transistor (TX431) on the left side of the tree is connected to the output of an AND gate, which consists of input diodes (D431, D432, . . . ) and resistor (RD41). True (IN PHASE) logic input signals (Z41, Z42, . . . ) are ANDed in this AND gate and a first elementary output signal, is available at the common emitter node (CN43) of the said differential pair. On the right side, additional inpout transistors (TX433, . . . ) are paralleled with the other input transistor (TX432) of the differential pair, so that the complementary (OUT OF PHASE) input signals (Z41, Z42, . . . ) that drive the transistors, are ORed to deliver a second elementary output signal, complementary to said first elementary output signal, on said common emitter node (CN43). Same principle applies at the first and second levels to build the bottom (44) and middle (45) stages. The present invention allows to increase the number of logical inputs to be applied to a DCCS logic circuit, and in turn, the number of logic functions performed in the logic DCCS tree. As a result, an extended library of DCCS logic circuits may be obtained.