The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 1991
Filed:
Jul. 30, 1990
Applicant:
Inventor:
Yukihiro Imura, Tokyo, JP;
Assignee:
Seiko Instruments Inc., , JP;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 52 ; 357 53 ; 357 54 ;
Abstract
A passivation layer covering a metal wire and semiconductor surface of a semiconductor integrated circuit composed of a metal-oxide-semiconductor (MOS) type transistor is a double-layer comprising a silicon nitride (P-SiN) layer formed by plasma CVD method and a phosphorus silicide glass (PSG) layer beneath the silicon nitride layer, and the P-SiN layer has a vacant region (a window) at the portion more than 20 .mu.m and less than 100 .mu.m away from an edge of a gate oxide layer of the transistor.
Imura, Yukihiro. (1991). Passivation layer structure with through-holes for semiconductor device (U.S. Patent No. 5070386). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5070386
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile