Method and circuit for detecting data error

Abstract

An error detecting circuit includes syndrome calculating circuits which calculates quotients S.sub.0 ', S.sub.1 ', S.sub.2 ' and S.sub.3 ' by division of syndromes. When all of the syndromes are '0', an error zero is detected by an error zero detecting circuit, and a signal is outputted. A single error detecting circuit detects a single error when S.sub.0 '=S.sub.1 '=S.sub.2 '=S.sub.3 '.noteq.0, outputting a signal. At this time, a J-latch holds a counted value 'j' of the counter which counts the number of the division as data indicative of an error position. Based upon data calculated by adding circuits and multiplying circuits, a double error detecting circuit detects that there are two or more errors through determination whether or not equations (S.sub.0 '+S.sub.1 ')(S.sub.2 '+S.sub.3 ')=S.sub.1 '+S.sub.2 ').sup.2 and (S.sub.0 '+S.sub.2 ')(S.sub.2 '+S.sub.3 ')=(S.sub.1 '+S.sub.2 ')(S.sub.1 '+S.sub.3 ') can be formed, outputting a detection signal when double errors occur. At this time, the J-latch and an i-latch hold counted values 'j' and 'i' as data indicative of error positions. By an error component calculating circuit, error components E.sub.i and E.sub.j are calculated by (S.sub.0 '+S.sub.1 ')/(1+.alpha..sup.i-j) and S.sub.0 -E.sub.i, respectively because a syndrome S.sub.0 =E.sub.i +E.sub.j.