The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 1991
Filed:
Oct. 02, 1989
Robert A Newman, Santa Clara, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A plastic encapsulated integrated circuit package is disclosed which comprises a multilayer ground plane assembly bonded to a lead frame with an integrated circuit die bonded to the composite assembly. The multilayer ground plane assembly is first formed by bonding together a copper sheet and a thermally conductive polyimide material insulating layer to which is also bonded a layer of a b-stage epoxy resin. The ground plane assembly is then bonded to the lead frame by placing the b-stage epoxy layer of the ground plane assembly against the lead frame and heating the ground plane assembly and lead frame to a temperature of from about 120.degree. C. to just under 200.degree. C. for a time period not exceeding about 10 seconds to bond the b-stage epoxy resin to the lead frame without oxidizing it. An integrated circuit die is then attached to the composite assembly with an epoxy adhesive and the die attached assembly is then cured in a non-oxidizing atmosphere in an oven at approximately 150.degree. C. for about 90 minutes to cure the adhesive and the b-stage epoxy layer. The die is then electrically connected to the lead frame. The bonded together ground plane/lead frame/die composite assembly is then placed in a mold and encapsulated in plastic. The integrated circuit structure of the invention has a lower average temperature rise per watt of power than prior art structures. Furthermore, logic-type plastic-encapsulated structures constructed in accordance with the invention have been found to operate at faster speeds due to lower inductance because of the presence of the copper ground plane layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile