The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 1991
Filed:
Sep. 07, 1989
Moritoshi Yasunaga, Kawaguchi, JP;
Noboru Masuda, Kokubunji, JP;
Hideo Todokoro, Tokyo, JP;
Yasunari Umemoto, Tokorozawa, JP;
Hirotoshi Tanaka, Yamanashi, JP;
Hiroyuki Itoh, Kodaira, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit device includes: input terminals; output terminals; a group of gates which receives an input signal applied to the input terminals and outputs an output signal from the output terminals, the output signal corresponding to the state of the input signal; and an arrangement for forcibly setting the output of each gate constituting the group either at a '1' level or at a '0' level irrespective of the state of the input signal and the state of an input signal to each gate. The arrangement for forcibly setting the output is an arrangement for changing the potential of a semiconductor substrate in which each gate is formed. This arrangement for changing potential includes an impurity doped region formed in the semiconductor substrate, the impurity doped region surrounding at least a transistor constituting each gate so as to apply a potential to the transistor, and a terminal for applying the potential to the impurity doped region. The semiconductor integrated circuit device according to another aspect includes an observation pad formed on a portion of at least one of the output and input areas of each gate, the observation pad being exposed without being covered with an insulator layer and the potential of the observation pad being observed as a difference of shading by using an electron or ion beam tester. A fault of each gate can be detected in accordance with a shading image of the observation pads.