Semiconductor memory device having a majority logic for determining data

Abstract

A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.