The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 1991
Filed:
Dec. 21, 1990
Shinri Fukuda, Tokyo, JP;
Eiichi Ishii, Tokyo, JP;
NEC Corporation, , JP;
Abstract
A transistor circuit has a first and a second transistor differentially connected with each other and having bases receiving an input signal therebetween; a first and a second resistor respectively connected between collectors of the first and second transistors and a first power supply terminal; a third transistor having an emitter receiving a voltage dropped by the first resistor and a collector connected to an output terminal; a fourth transistor having an emitter receiving a voltage dropped by the second resistor; and a fifth transistor having a collector connected to the output terminal and an emitter connected to the second power supply terminal. Biasing voltages are provided to bases of the third and fourth transistors thereby causing the fourth transistor to be conductive when the voltage dropped by the first resistor is larger than the voltage dropped by the second resistor and causing the third transistor to be conductive when the voltage dropped by the first resistor is smaller than the voltage dropped by the second resistor. The fifth transistor become conductive when the fourth transistor is in a conductive state. The circuit is capable of operating in a high speed and the output amplitude is such that the low level can be lower to a point just before the saturation of the fifth transistor and the high level can be raised near to the power supply voltage. The power supply voltage required to the circuit is substantially reduced.