Semiconductor storage device

Abstract

Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are prechanged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory. The memory array is implemented in a semiconductor storage device, such as a static RAM, which is characterized as operating either as a one-port or two-port system and wherein it, furthermore, employs a write amplifier circuit arrangement and a sense amplifier arrangement, such as of the single-ended differential type, wherein the write and sense amplifier arrangements can be disposed either on separate common data lines or on a single common data line.