Video signal processor for simultaneously reproducing a plurality of

Abstract

A video signal processing apparatus which includes a clock signal generator for generating a clock signal in synchronism with a color synchronizing signal contained in an incoming video signal. This clock signal has a frequency equal to a multiple of the frequency of the color synchronizing signal. An analog-to-digital converter operates in response to the clock signal to sample and convert an incoming composite video signal into a digital video signal. An address setting circuit is provided for generating an address signal synchronized with horizontal and vertical synchronizing signals. The apparatus also includes a memory having addresses controlled by the address signal, a write-in device for writing bits extracted out of a digital output signal from the analog-to-digital converter into the memory in synchronism with the clock signal, a read-out device having addresses adapted to be controlled by the address signal and for reading out a digital signal from the memory in synchronism with the color synchronizing signals, and a digital-to-analog converter for converting the read digital signal read into an analog signal. The bits have phases different from that of the color synchronizing signal, the differences in phase between the bits and the color synchronizing signal being continued at a predetermined bit interval.