The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 1991
Filed:
Mar. 20, 1991
Patrick Lamey, Manassas, VA (US);
Richard Kachmarik, Bealeton, VA (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
A method to integrate thermal drop on demand ink jet devices and related pulse driver circuitry for chips used in thermal ink jet printers. This integrated printhead chip is made by first fabricating on the substrate the driver pulse circuitry through the last level of metallization. Once complete, a low temperature (<400 C) CVD oxide is deposited and planarized. It is of sufficient thickness (3 to 4 microns) to insure a good thermal barrier between the pulse circuitry and the thermal inkjet devices. After planarization, the resistor material is deposited and patterned. Openings are then patterned to the inputs and outputs of the pulse driver circuitry. Aluminum copper metallurgy is deposited and patterned to connect the resistor to the pulse driver output and define the heater resistor areas. Inorganic and organic barrier layers are applied and patterned to protect the resistor material and interconnecting metallurgy from the corrosive effects of the ink. After testing, ink holes are drilled and the wafer is diced and nozzle plates are attached to the chips. Thus, this 'on chip' driver integration enables the pulse driver circuitry to be moved to the thermal ink jet printhead. It offers advantages over other methods of ink jet/driver device integration by the chip footprint the same without decreasing the dimensions of the respective devices.