Reprogrammable logic fuse based on a 6-device sram cell for logic arrays

Abstract

A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell includes a storage element comprised of four cross coupled FETs. A fifth FET is mounted in a transmission gate configuration between the bit line and a first common node of the storage element. Its gate electrode is connected to the word line. This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET is also mounted in a transmission gate configuration between the second common node of the storage element and an output line. Its gate electrode is connected to the input line. This sixth FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at the second common node and on the input line. Other configurations of said sixth FET are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs). In the latter case, in the AND array the input and output lines are respectively the product term lines (if bit partitioning is employed) and AND term lines (or Match Lines). In the OR array, the input and output lines are respectively the Match Out lines (the signal on the Match Line after complementation) and the OR out lines. RPLAs employing these RLF's can be dynamically reprogrammed to allow in system logical reconfiguration in real time.