The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 1991

Filed:

Nov. 03, 1989
Applicant:
Inventors:

William M Peterson, Scottsdale, AZ (US);

Christopher N Hume, Mesa, AZ (US);

Robert H Leivian, Chandler, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395 27 ; 365 49 ;
Abstract

A random access memory (RAM) circuit is provided wherein an input signal matrix forming an identifiable original pattern is learned and stored such that a distorted facsimile thereof may be applied to generate an output signal matrix forming a replication of the original pattern having improved recognizable features over the distorted facsimile. The input signal matrix is logically divided into a plurality of predetermined subsets comprising a unique element of the input signal matrix and the elements in the neighborhood thereof. Each predetermined subset is quantized into a first digital address and applied at the address inputs of a memory circuit for retrieving data stored in the addressed memory location, while one signal of the predetermined subset is digitized and weighted and combined with the data retrieved from the addressed memory location for storage in the same addressed memory location. Next, a plurality of second digital addresses is generated including predetermined combinations of the first digital address perturbed at least one bit and sequentially applied at the address inputs of the memory circuit whereby the steps of digitizing and weighting one signal of the predetermined subset of the input signal matrix, combining the digitized and weighted signal with the data retrieved from the addressed memory location, and storing the combination back into the addressed memory location are repeated for the second digital addresses.


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