The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 1991
Filed:
Sep. 18, 1990
Ying-Cheng Chen, Hsinchu, TW;
Bau-Tong Dai, Hsinchu, TW;
Abstract
An FET ROM and a manufacturing process in which ROM's can be stockpiled after the gates have been formed and the source and drain implants have been made but before the write operation has been performed. At this stage, the unwritten ROM has an array of enhancement mode FET's connected in a logical NAND configuration with an overlying layer of insulation. For a write operation, the insulation is removed to expose the drain and source regions of the FET's, a conductive layer is formed over the array, and the layer is selectively etched to leave a short circuit element between the drain and source of those FET's that are to store a binary 0 and to leave switchable the FET's that are to store a 1.