The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 1991

Filed:

Dec. 07, 1989
Applicant:
Inventors:

Thomas J Aton, Dallas, TX (US);

Satwinder Malhi, Garland, TX (US);

Masashi Hashimoto, Garland, TX (US);

Shivaling S Mahant-Shitti, Bangalore, IN;

Oh-Kyong Kwon, Richardson, TX (US);

Thirumalai Sridhar, Huston, NH (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
3241 / ; 3241 / ; 324512 ; 324537 ;
Abstract

A system and method for testing the continuity of interconnecting nets on a substrate to be used in multi-chip technology is provided. The system includes coupling a test pad (15) to the net (12) to be tested. The test pad (15) is coupled through a diode (34) to a common node (32). The voltage of a first node (16) of the net (12) is sensed by a voltmeter (38) which is coupled to ground. A predetermined current signal is applied to each node (16, 18, 20, 22) in the net through the use of a probe (42). The voltage of the remaining nets (14) is sensed by a voltmeter (44). If an erroneous interconnection (31) is present between the net (12) to be tested and any other net (14) on the substrate, the voltage of the other net (14) will fluctuate. The voltmeter (38) will indicate if there is an electrical connection between the node (16) and the test pad (15) during testing. If an electrical path is established between each node in the net (12) and test pad (15), the continuity of the net (12) is established through the operation of Ohm's law.


Find Patent Forward Citations

Aton, Thomas. (1991). Method and apparatus for testing passive substrates for integrated (U.S. Patent No. 5059897). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5059897

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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