The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 1991

Filed:

Jun. 04, 1987
Applicant:
Inventors:

Donald K Lauffer, Poway, CA (US);

Ikuo J Sanwo, San Marcos, CA (US);

Assignee:

NCR Corporation, Dayton, OH (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01H / ; H03K / ;
U.S. Cl.
CPC ...
307576 ; 3072021 ; 307451 ; 307469 ; 307464 ; 307475 ;
Abstract

A CMOS circuit having an input threshold, the CMOS circuit including a first field-effect transistor having a source connected to a first power supply terminal, a drain connected to an output terminal, a gate connected to an input terminal, and a first channel between the source and the drain having a first width and a first length. A programmable field-effect transistor circuit has a gate terminal connected to the input terminal, a drain terminal connected to the output terminal, a source terminal connected to a second power supply terminal, and a second channel circuit between the drain terminal and the source terminal having an effective width and an effective length. Programmable input terminals are connected to the second channel circuit for changing the ratio of the product of the first width times the effective length to the product of the effective width times the first length such that the input threshold voltage of the CMOS circuit is changed responsive to the change of the ratio. By programming the input terminals and selecting the voltages on the first and second power supply terminals, a universal input buffer for conversion of one logic level voltage to another may be provided.


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