Supply bounce controlled output buffer circuit

Abstract

A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin with a significant reduction in inductive ringing includes an output stage, a first delay network (38), and a second delay network (42). The output stage includes a series-connected pull-up transistor (P1) and pull-down transistor (N1) coupled between a first power supply terminal pin and a second power supply terminal pin. The common connection of the pull-up and pull-down transistors (P1, N1) are coupled to an output terminal pin. The first delay network (38) is interconnected between the first power supply terminal pin and a control electrode of the pull-up transistor (P1) for turning off the pull-up transistor (N1) so as to slow down the rate of rise of the output signal for a portion of the time when the output terminal pin is making a low-to-high transition so as to reduce the overshoot. The second delay network (42) is interconnected between the second power supply terminal pin and a control electrode of the pull-down transistor (N1) for turning off the pull-down transistor (N1) so as to slow down the rate of fall of the output signal for a portion of the time when the output terminal pin is making a high-to-low transition so as to reduce the undershoot.