Cmos ram having a complementary channel sense amplifier

Abstract

A semiconductor memory such as a dynamic RAM (Random Access Memory) implemented by complementary MOS (CMOS) transistors includes a plurality of bit line pairs each constituted by a first and a second complementary bit line for transferring data, and a plurality of word lines extending across the bit line pairs. A plurality of memory cells are located at the intersecting points of the bit line pairs and word lines and connected to the latter for storing data therein. A plurality of sense amplifier circuits are each associated with respect to one of the bit line pairs for sensing potentials on a first and a second node associated with the bit line pair and amplifying the sensed potentials. Each of the sense amplifier circuits includes a first and a second sense amplifier of opposite polarity. A plurality of first field effect transistors (FETs) each has a source-drain path for connecting to the first node the first bit line of respective one of the bit line pairs. A plurality of second FETs each has a source-drain path for connecting to the second node the second bit line of respective one of the bit line pairs. The plurality of first and second field effect transistors individually have commonly connected control electrodes to which a gate signal is applied. The plurality of first and second field effect transistors are complementarily controlled in response to the gate signal to transfer one of the potentials on the first and second bit lines to one of the first and second sense amplifiers.