Address register processor system

Abstract

A digital processing system comprising a source of input data for producing digital information, a data queue connected to the data input by a data bus, a memory array interactive with the data queue, a memory controller connected to the data queue into the memory array for timing the read/write signal cycles of the memory array in response to the state of the data queue, and a data output receiver connected by a data bus to the data queue. The data queue performs serial-to-parallel conversion of the input data from the input data source. The data queue also performs parallel-to-serial conversion on the output data to the data output receiver. The input data source comprises a large contiguous block of memory data connected to the data queue by a plurality of ports. Each of the ports is independent of any of the other ports. The data queue is a loadable shift register having a plurality of data paths extending from the input data source, the memory controller, and the data output receiver. The memory array has a data path width equivalent to the data path width of the data queue.