Two-dimensional array of processing elements for emulating a

Abstract

Two-dimensional mesh architecture in an array processor of myriad processing elements allows relative ease in manufacturing, using planar integrated circuits and predominant X, Y connections. There is a need, in any array processor, to connect a selected processing element to another processing element. Rather than to supply the large number of connectors required for dedicated connection of processing element to processing element, implementation is by a very limited number of connecting conductors (NESW) in a two-dimensional mesh. The connecting conductors are coplanar, making construction compatible with present-day, essentially planar and predominantly XY, packaging of integrated circuits and printed circuit boards. Flexibility of interconnection by means of this limited and inflexible set of conductors is accomplished by equipping each processing element with a hopping circuit. This is an advantageous tradeoff of silicon area, since the few active elements of the hopping circuit consume much less silicon area than the large number of conductors otherwise required. The hopping circuits are programmable, by a shared routing controller, to send input to an internal register file within the processing element, or to respond to a HOP (direction)(step) command. The HOP command selects the direction parameter by selecting one of the limited external connections to an adjacent processing element. Connection to a remote processing element requires a number of HOP command steps, carried out in a series of cycles. Each hopping circuit includes multiplexer, sink register, demultiplexer and gates.