The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 1991

Filed:

Jun. 19, 1990
Applicant:
Inventors:

Hideki Miyazaki, Hitachi, JP;

Akihiko Kanouda, Hitachi, JP;

Kozo Watanabe, Hitachi, JP;

Kenichi Onda, Hitachi, JP;

Yasuo Matsuda, East Chaester, NY (US);

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307571 ; 307451 ; 307530 ; 307270 ; 307576 ; 307285 ; 3072961 ; 330257 ;
Abstract

The switching of the positive (or pullup power) and negative (or pulldown power) semiconductor elements, are controlled by driving circuits which are in turn controlled by level shift circuits which have a first current control circuit and a second current control circuit coupled in parallel and this parallel connection is coupled in series with the control N-channel MOSFET of a current mirror circuit in a circuit loop arrangement with a control power supply. The first and second current control circuits are responsive to first and second control pulses of pulse widths t.sub.1 and t.sub.1 +t.sub.2, in accordance with a driving signal such that the first current control circuit supplies a first current level to the control N-channel MOSFET during the first time period t.sub.1 and the second current control circuit supplies a second current level, smaller than that of the first current level, thereto for a predetermined time period t.sub.1 +t.sub.2 thereby resulting in a current flow through the controlled N-channel MOSFET of the current mirror circuit of a current value corresponding to the sum of the first and second current levels. The controlled N-channel MOSFET, providing ON/OFF control of a P channel MOSFET, is disposed in a second circuit loop which is powered by a high voltage power supply. This P-channel MOSFET, coupled to the high voltage power supply, supplies an output signal to a load in response to the current flowing through the controlled N-channel MOSFET.


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