The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 1991
Filed:
Feb. 28, 1990
Masahiro Iwamura, Hitachi, JP;
Akira Ide, Takasaki, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
An invention is disclosed, which is suitable for operating a bipolar-MOS logic circuit, and in particular Bi-CMOS logic circuit with a low power supply voltage below 5V, e.g. around 3V. According to the present logic circuit, since the base current of a second NPN transistor is supplied from a power supply through a PMOS transistor (first current switching means), the impedance of which is lowered previously by a logic inverting means and an NMOS logic circuit (second current switching means), which is on/off controlled by an input signal, in a transient logic level transition period where the output is switched from the level '1' to '0' (i.e. it falls), it is possible to supply a sufficient base current to the second NPN. In this way, it is possible to turn-on the second NPN with a high speed and to pull down to the level '0' with high speed. Further, since the PMOS is switched off owing to the action of the logic inverting means just after having allowed a sufficient base current flow therethrough, the current path, through which the base current of the second NPN is supplied, is stopped and thus DC power consumption is elimated.