Architectures for serial or parallel loading of writable control store

Abstract

A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor. One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus. This processor can receive programs either over the serial loop or over the cache bus. The use of the wide cache bus for parallel microinstruction transfer permits fast microcode overlaying. This system even makes dynamic paging of microcode practical in some applications.