Direct memory access controller with expedited error control

Abstract

A direct memory access (DMA) controller is adaptable to control a DMA which is independently made in a plurality of channels of a data processing apparatus, where the plurality of channels have predetermined priority sequences and the DMA controller includes a bus and terminal controller coupled to a system bus for obtaining a right to use the system bus responsive to a transfer request, an interrupt and slave controller coupled to the system bus for controlling an interrupt which is made to a central processing unit (CPU) when a data transfer ends for each of the plurality of channels and for controlling an access from the CPU, and an operation determination part for determining an operation of the DMA controller depending on the transfer request, whether or not the bus and terminal controller obtained the right to use the system bus and whether or not the access is made from the CPU. The slave and interrupt controller includes an interrupt controller for supplying to the CPU an interrupt of a channel in which an abnormal end of a data transfer has occurred with a priority over other channels in which a normal end of a data transfer has occurred regardless of the priority sequences of the plurality of channels.