The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 1991

Filed:

May. 09, 1990
Applicant:
Inventors:

Kazuo Tanaka, Tokyo, JP;

Masato Hamamoto, Tokyo, JP;

Toshio Yamada, Tokyo, JP;

Tohru Kobayashi, Iruma, JP;

Hiromasa Katoh, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01K / ; G06F / ;
U.S. Cl.
CPC ...
3073031 ; 3074821 ; 3072721 ; 307465 ;
Abstract

Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.


Find Patent Forward Citations

Tanaka, Kazuo. (1991). Integrated logic circuit having plural input cells and flip-flop and (U.S. Patent No. 5055710). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5055710

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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