The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 1991
Filed:
Jan. 26, 1989
Yoichi Tobita, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In a semiconductor memory device having a test mode setting circuit, when a voltage higher than a common operation range is applied to an input terminal (101) receiving CAS signals, a first voltage detecting circuit (100) detects the voltage and the detected output is latched in a latch circuit (110). A voltage setting circuit (1 20) sets a cell plate voltage of a memory cell (1a) approximately at the ground potential in response to the latch output. Consequently, the operation margin of the memory cell for the data '1' can be carried out by the V bump test. Meanwhile, when a voltage higher than the normal operation range is applied to an input terminal (201) receiving WE signals, a second voltage detecting circuit (200) detects the voltage and the detected output is latched in the latch circuit (201). The voltage setting circuit sets the cell plate voltage approximately at Vcc in response to the latch output from the latch circuit.