The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 1991

Filed:

Mar. 18, 1988
Applicant:
Inventors:

Elliot L Gould, Colchester, VT (US);

Douglas W Kemerer, Essex Junction, VT (US);

Lance A McAllister, Williston, VT (US);

Ronald A Piro, South Burlington, VT (US);

Guy R Richardson, Milton, VT (US);

Deborah A Wellburn, Colchester, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; G06F / ;
U.S. Cl.
CPC ...
364489 ; 364488 ; 437 56 ; 437 74 ; 357 42 ; 357 45 ; 357 47 ; 357 52 ;
Abstract

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.


Find Patent Forward Citations

Loading…