High voltage system using enhancement and depletion field effect

Abstract

An enhancement mode field effect transistor and a depletion mode field effect transistor are connected in a circuit to provide for a conductivity of the transistors during a first polarity in an alternating voltage and to provide for a non-conductivity of the transistors during a second polarity in the alternating voltage. The circuit also provides for the continued and proper operation of the circuit even when voltages having a magnitude greater than the breakdown voltage of the enhancement mode field effect transistor are applied to the circuit. Each of the transistors may have a source, a gate and a drain. The gates of the transistors receive an alternating voltage of one polarity at the same time that the drain of the depletion mode field effect transistor receives a voltage of the opposite polarity. The source of the depletion mode field effect transistor and the drain of the enhancement mode field effect transistor are common. The source of the enhancement mode field effect transistor may receive a reference potential such as ground. The transistors are conductive during the application of a positive voltage to their gates and are non-conductive during the application of a negative voltage to their gates. When the transistors are non-conductive, the depletion mode transistor prevents the voltage on the drain of the enhancement mode field effect transistor from exceeding the breakdown value.