The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 1991
Filed:
Feb. 22, 1991
Gensuke Goto, Ebina, JP;
Hajime Kubosawa, Machida, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An operation circuit for M-bits parallel full addition includes partitioned adders and first and second multiplexers. Each of the first multiplexers selects one of paired provisional carry signals C.sub.ns-1 (1) and C.sub.ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C.sub.(s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C.sub.ns-1 to be progatatd from the s-th partitioned adder. Each of the second multiplexers generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k=n(s+1)-1, n(s+2) -1, . . . , n(s+l)-1) by referring to paired provisional carry signals Cr(1) (or Cr*(1); r=k-n=ns-1) and Cr(0) (or Cr*(0); k-n=ns-1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate l real carry signals Ck at the same time by selecting either the provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C.sub.(s-1)n-1 relating to a digit which is one digit lower than the lowest-order digit of the s-th partitioned adder.