Asynchronous microprocessor random access memory arbitration controller

Abstract

a system of arbitration for access to a common memory by two asynchronous microprocessors without excluding either microprocessor for more than a predetermined, limited period of time. Two asynchronous microprocessors are connected to a common memory through an arbitration controller with a connection to transmit a 'not ready' signal to one microprocessor requesting access when the other is in the process of accessing the common memory. A flip flop is connected to generate a predetermined signal output when a microprocessor requires access to the common memory, and this predetermined signal initiates a shift register to provide the internal timing of the asynchronous microprocessor requiring such access to bring it into synchronism with the clock controlling the internal cycle of the common memory. When there is contention for access to the common memory, a flip flop connects one microprocessor to the common memory, where such connection is maintained only for a predetermined, limited period of time, when access is returned to the first microprocessor. Access to the common memory by any microprocessor is always for only this one, predetermined, limited period of time.