The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 1991

Filed:

Mar. 31, 1989
Applicant:
Inventors:

Rohit L Bhuva, Plano, TX (US);

Walter C Bonneau, Jr, Peoria, AZ (US);

Robert L Gruebel, Plano, TX (US);

Robert A Helmick, Allen, TX (US);

Allen Y Chen, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; G06F / ;
U.S. Cl.
CPC ...
307475 ; 307455 ; 307456 ; 307465 ; 307443 ;
Abstract

A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high value in response to one of the high and low values of the true ECL signal, and a low value in response to the other of the high and low values of the true ECL signal. A first translator circuit (36, 64) has an input (32) coupled to the differential circuit (180). The first translator circuit (36, 64) transmits a true low TTL output (56) signal having a voltage level referenced to the voltage level of a TTL low supply voltage in response to receiving a high value of the differential signal. A second translator circuit (46, 52) has an input (38) and is coupled to a TTL high supply voltage and the output (56). An input signal appearing on the input (38) of the second translator circuit has a voltage level related to the voltage level of the differential signal (32). The second translator circuit (46, 52) transmits a high TTL output signal having a voltage level referenced to the voltage level of the TTL high supply voltage in response to the differential signal (32) being at a low value.


Find Patent Forward Citations

Loading…