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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5047669 B1

PDFFull Text
Date of Patent:
Sep. 10, 1991

Filed:

Mar. 03, 1989

Tristate circuit using bipolar transistor and cmos transistor

Applicant:
Inventors:

Masahiro Iwamura, Hitachi, JP;

Kozaburo Kurita, Hitachi, JP;

Hideo Maejima, Hitachi, JP;

Tetsuo Nakano, Ome, JP;

Atsuo Hotta, Higashiyamato, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:

Antonelli, Terry, Stout & Kraus

Primary Examiner:

David Hudspeth

Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307446 ; 307443 ; 307473 ;
Abstract

In a semiconductor integrated circuit, drain-source paths of an NMOS transistor and a PMOS transistor are connected between the base and emitter of a bipolar transistor, and control signals are applied to gates of the NMOS transistor and the PMOS transistor so as to keep the NMOS transistor and the PMOS transistor at OFF condition when the bipolar transistor is operating and so as to keep the NMOS transistor and the PMOS transistor at ON condition when the bipolar transistor is in the quiescent state.

Find Patent Forward Citations

Iwamura, Masahiro. (1991). Tristate circuit using bipolar transistor and cmos transistor (U.S. Patent No. 5047669). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5047669

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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