The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 1991
Filed:
Feb. 28, 1990
Robin J Jigour, San Jose, CA (US);
Shueh-Mien J Lee, Sunnyvale, CA (US);
Ali Pourkeramati, Santa Clara, CA (US);
ICT International CMOS Tech., Inc., San Jose, CA (US);
Abstract
A programmable logic device having greater design flexibility through use of a plurality of programmable macrocells in conjunction with programmable gate arrays. Each macrocell includes a programmable reconfigurable register for receiving sum terms from the array, and an I/O terminal connected to receive an output from the programmable reconfigurable register. Two separate feedbacks from the macrocell to the gate array are provided. The first feedback has multiple inputs including the register output, and the second feedback has multiple inputs including the I/O terminal. Accordingly, the I/O terminal and the register can function independently. Each sum term is capable of serving multiple functions as determined by the programming of the macrocell whereby the input terms can be utilized to implememt two completely independent sum-of-product logic functions, both combinatorial and one combinatorial and one sequential, and whereby each is capable of being programmably routed as feedback to the array or as an output to the I/O terminal.